Technische Daten

• Minimum 2-channel, 14-bit, 125-MSPS ADC
• Minimum 2-channel, 16-bit, 500-MSPS
• Minimum of two Xilinx Virtex-4 LX80, LX100, or LX160 FPGA
• Minimum of four Texas Instruments C6416 DSP
• real-time data exchange tools with the host device CPU
• Real-time and hardware-in-the-loop co-simulation capabilities
• DSP-FPGA video framework through a four-port SDRAM FPGA core
• Complete model-based design flow support
• Language-based design flow
• Recording and playback tools
• Direct and remote access capabilities